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| www..com ZEN2044F PROGRAMMABLE UNIVERSAL COUNTER DESCRIPTION The ZEN2044F is a 24bit x 4ch. programmable universal counter LSI. The ZEN2044F can count phase-shifted pulse signals or up/down pulse signals generated from rotary encoders or linear scales. Since the counter response speed is as high as 33MHz(MAX), the ZEN2044F can be used in a variety of applications required high speed counting, including digital servo controls and precision measurements. As to command sets, the ZEN2044F has a compatibility with the ZEN2011P. The ZEN2044F can also monitor input signals and detect any abnormal input accompanied with noise or other disturbances, so that the reliability of counted values are secured. Pin Configuration(Top View) B/DN2 A/UP2 Vss SEL22 SEL21 SEL20 LT2 LD2 Vss EXTA2 EXTB2 Vdd Vdd CLK Vss DIR1 UD/AB1 Z/CLR1 B/DN1 A/UP1 n.c. SEL12 SEL11 SEL10 LT1 LD1 Vdd EXTA1 EXTB1 Vss 1. Features 80 24bit binary up/down counter x 4ch. 81 Z/CLR2 80 75 70 65 60 Counter response speed: UD/AB2 DIR2 33MHz(MAX)(CLK fo=33MHz at 50% duty) Vdd EXTB3 85 EXTA3 Input frequency of count pulse Vss LD3 LT3 Two phase-shifted pulse signal input: Vss 90 Vdd DC-8.25MHz (less than fo x 1/4) SEL30 SEL31 SEL32 Up/down pulse signal input: 95 Vss A/UP3 DC-16.5MHz (less than fo x 1/2) B/DN3 Z/CLR3 Vdd Direction recognition for up/down count 5 10 15 20 n.c. 100 100 Abnormal input detection circuit 1 Preload register for the up/down counter Latch register for the up/down counter Coincidence detection between reference value and count value Counter operation mode Quad/double/single edge evaluation(for two phase-shifted signal / single pulse signal) Counter direction selection Count clear control: synchronous/asynchronous Command mode Mode 0: Each channel has one comparator for coincidence detection Each channel has one port for user input Mode 1: Each channel has two comparators for coincidence detection Each channel has no port for user input Logical sum output of coincidence detections available Interrupt output under some conditions available 8bit data bus Low power CMOS technology TTL level compatible input Single 5V power supply 100 pin QFP Note ) In following chapters; "n" corresponds to a number of the channel(0-3). "*" stands for "Don't care". 51 50 55 50 n.c. Vss TEST1 TEST0 Vss D7 D6 D5 D4 Vdd Vss D3 D2 D1 D0 Vdd RD WR Vss n.c. 45 40 35 25 30 -1- n.c. UD/AB3 DIR3 Vss EXTB0 EXTA0 Vdd LD0 LT0 SEL00 SEL01 SEL02 TESTI n.c. Vss RESET Vdd A/UP0 B/DN0 Z/CLR0 UD/AB0 DIR0 n.c. Vss C/D AD/CE0 AD/CE1 AD/CE2 AD/CE3 DRCTCE 31 30 (Z2044G00)ZENIC INC. www..com ZEN2044F 2. Block diagram DRCTCE AD/CE[3:0] C/D WR RD LT0 LD0 CPU I/F CE C/D WR RD LT LD SEL[2:0] UD/AB DIR A/UP B/DN Z/CLR D[7:0] Direction recognition for up/down rd Command wr decoder lt ld Ch.0 Status reg. (8bit) Reference reg.A(24bit) Reference reg.B(24bit) Up/down counter (24bit) Preload reg. (24bit) cnt0 Ch.1 CE C/D WR RD LT LD SEL[2:0] UD/AB DIR A/UP B/DN Z/CLR D[7:0] c n t 1 EXTA EXTB EXTA1 EXTB1 Mode0,1 function control Comparator A(24bit) Comparator B(24bit) Latch reg.(24bit) EXTA EXTB EXTA0 EXTB0 SEL0[2:0] UD/AB0 DIR0 A/UP0 B/DN0 Z/CLR0 D[7:0] LT1 LD1 SEL1[2:0] UD/AB1 DIR1 A/UP1 B/DN1 Z/CLR1 Ch.2 CE C/D WR RD LT LD SEL[2:0] UD/AB DIR A/UP B/DN Z/CLR D[7:0] c n t 2 EXTA EXTB EXTA2 EXTB2 LT3 LD3 SEL3[2:0] UD/AB3 DIR3 A/UP3 B/DN3 Z/CLR3 CE C/D WR RD LT LD SEL[2:0] UD/AB DIR A/UP B/DN Z/CLR D[7:0] Ch.3 c n t 3 EXTA EXTB EXTA3 EXTB3 LT2 LD2 SEL2[2:0] UD/AB2 DIR2 A/UP2 B/DN2 Z/CLR2 CLK RESET Vdd Vss -2- (Z2044G00)ZENIC INC. www..com ZEN2044F 3. Pin description Table 1 Name EXTA0 EXTA1 EXTA2 EXTA3 No. 6 53 71 86 I/O O Function The function of this output depends on the command mode. In Mode 0, EXTAn outputs the equal signal A(EQAn). In Mode 1, one of the following three signals can be selected: -The equal signal A(EQAn). -The logical sum(EQAn +EQBn) of the equal signal A(EQAn) and the equal signal B(EQBn). -The hold equal signal A(INTEQAn). The CLK synchronizes the internal circuit operation. The RESET initializes the up/down counter, the phase discrimination circuit, the command register and the status register. The function of these pins depends on the DRCTCE. If DRCTCE="1", they are all treated as signals for enabling the channel directly. If DRCTCE="0",AD/CE3 and AD/CE2 are the chip enable pins and AD/CE1 and AD/CE0 are used to select the channnel. The DRCTCE specifies the mode of the channel select. The C/D defines the type of the data transfered between the CPU and the ZEN2044F(command or value). This pin is usually connected with LSB of the address lines. The RD is the strobe signal of the read operation. The WR is the strobe signal of the write operation. The LDn transmits the 32bit data which is stored in the preload register to the up/down counter. CLK RESET AD/CE0 AD/CE1 AD/CE2 AD/CE3 DRCTCE C/D 67 16 26 27 28 29 30 25 I I I I I RD WR LD0 LD1 LD2 LD3 LT0 LT1 LT2 LT3 D0 D1 D2 D3 D4 D5 D6 D7 EXTB0 EXTB1 EXTB2 EXTB3 34 33 8 55 73 88 9 56 74 89 36 37 38 39 42 43 44 45 5 52 70 85 I I I I The LTn stores the 32bit data of the up/down counter into the latch register. I/O These pins are connected with CPU data bus. I/O In Mode 0, EXTBn is used as a general purpose input U of which value can be read from the status register. In Mode 1, EXTBn is a programable output. One of the following three signals can be selected: -The equal signal B(EQBn) -The signal that indicates detecting an abnormal input(INTAIn) -The hold equal signal B(INTEQBn) -3- (Z2044G00)ZENIC INC. www..com ZEN2044F Name Z/CLR0 Z/CLR1 Z/CLR2 Z/CLR3 B/DN0 B/DN1 B/DN2 B/DN3 A/UP0 A/UP1 A/UP2 A/UP3 SEL00 SEL01 SEL02 SEL10 SEL11 SEL12 SEL20 SEL21 SEL22 SEL30 SEL31 SEL32 DIR0 DIR1 DIR2 DIR3 UD/AB0 UD/AB1 UD/AB2 UD/AB3 Vss No. 20 63 81 98 19 62 80 97 18 61 79 96 10 11 12 57 58 59 75 76 77 92 93 94 22 65 83 3 21 64 82 2 4 15 24 32 40 46 49 51 66 72 78 87 90 95 I/O I Function The Z/CLRn clears the value of the up/down counter. This pin is usually connected with the index signal of a rotary encoder or a linear scale. The B/DNn is the count pulse input B or DN. I I The A/UPn is the count pulse input A or UP. I The condition of these three pins(SELn0, SELn1 and SELn2) specifies the counter operation mode. See the Table 4. I The DIRn selects the count direction of the up/down counter. I The UD/ABn selects the input pulse mode(up/down or not). - Ground(0V) -4- (Z2044G00)ZENIC INC. www..com ZEN2044F Name Vdd No. 7 17 35 41 54 68 69 84 91 99 1 14 23 31 50 60 100 47 48 13 I/O Supply voltage(+5V) Function N.C. - Not connected. TEST0 TEST1 TESTI I These test pins MUST be connected with +5V in nomal operation. Note ) Except N.C., the input pins which are not used MUST be connected with Vdd or Ground. ZEN2044F -5(Z2044G00)ZENIC INC. www..com 4. Operation The opration of the ZEN2044F is controled by the system software. To use this counter, it is necessary to specify "command words","counter reference value(if necessary)" and "preloaded value(if necessary)". Since the entire control circuit woks synchronously, the operations about registers(i.e. data read/write, command write and status read) can be carried out even if the counter is working. Each channel can be programed separately because the ZEN2044F has four fully independent sets of the counter and the registers. 4-1. CPU Interface The CPU can access the ZEN2044F with AD/CE3-0, C/D, RD and WR. The ZEN2044F has following two modes for selecting the target channel. The mode depends on DRCTCE. 4-1-1. Direct Channel Enable Mode(DRCTCE="1") In this mode, AD/CEn is used as the channel enable input for channel n . So multiple channels can be accessd at a time(write operation only). Table 2 DRCTCE AD/CE3 AD/CE2 AD/CE1 AD/CE0 C/D RD WR Function 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 * * * 0 1 1 1 0 * * * 0 1 1 1 0 1 * * 0 * 1 1 0 1 * * 0 * 1 1 0 1 1 * 0 * * 1 0 1 1 * 0 * * 1 0 1 1 1 0 * * * 0 1 1 1 0 * * * * 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 * 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 * 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Disable(data bus: High-impedance) Read: latch register(ch.0) Read: latch register(ch.1) Read: latch register(ch.2) Read: latch register(ch.3) Write: data for registers(ch.0) Write: data for registers(ch.1) Write: data for registers(ch.2) Write: data for registers(ch.3) Read: status register(ch.0) Read: status register(ch.1) Read: status register(ch.2) Read: status register(ch.3) Write: command(ch.0) Write: command(ch.1) Write: command(ch.2) Write: command(ch.3) ZEN2044F -6(Z2044G00)ZENIC INC. www..com 4-1-2. Normal Addressing Mode(DRCTCE="0") In this mode, A pair of AD/CE3 and AD/CE2 is used as the chip enable input for the ZEN2044F and the lower two bits(AD/CE1 and AD/CE0) specify the target channel. Table 3 DRCTCE AD/CE3 AD/CE2 AD/CE1 AD/CE0 C/D RD WR Function 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 * * * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 * * * 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 * * * 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Disable(data bus: High-impedance) Disable(data bus: High-impedance) Disable(data bus: High-impedance) Read: latch register(ch.0) Read: latch register(ch.1) Read: latch register(ch.2) Read: latch register(ch.3) Write: data for registers(ch.0) Write: data for registers(ch.1) Write: data for registers(ch.2) Write: data for registers(ch.3) Read: status register(ch.0) Read: status register(ch.1) Read: status register(ch.2) Read: status register(ch.3) Write: command(ch.0) Write: command(ch.1) Write: command(ch.2) Write: command(ch.3) ZEN2044F -7(Z2044G00)ZENIC INC. www..com 4-2. Command mode The ZEN2044F has the following two system modes. First of all, it is necessary to determine which mode you use(Mode 0 or Mode 1). The system mode is fixed by executing the system mode set command (90H or 91H). 4-2-1. Mode 0 [after executing command(90H) or system reset] EXTBn is set as a universal input terminal U. One set of the refrence register and the comparator is available. 4-2-2. Mode 1 [after executing command(91H)] EXTBn is set as an output terminal. Both EXTAn and EXTBn can be controled by the instruction sets of Mode 1. And two sets of the refrence register and the comparator are available. 4-3. Selection of counter operation mode The type of counter pulse and the mode of clearing counter by Z input depend on the condition of UD/ABn, SELn0, SELn1 and SELn2(these signals should be static and not set by the CPU). Refer to Table 4 for detail. Table 4 UD/ABn 1 SELn2 * 0 0 0 0 1 1 1 0 1 SELn1 * 0 0 1 0 0 1 1 1 SELn0 * 0 1 0 0 1 0 1 1 Pulse input(Edge eval.) Up/down pulse Phase-shifted(single) Phase-shifted(double) Phase-shifted(quad) Phase-shifted(single) Phase-shifted(double) Phase-shifted(quad) Single pulse(single) Single pulse(double) Asynchronous clear Asynchronous clear Synchronous clear Clear mode Asynchronous clear -8- (Z2044G00)ZENIC INC. www..com ZEN2044F 4-4. Pulse count timing(Edge evaluation) The following diagrams show how an edge of the input pulse is evaluated in each count operation mode. "1" means counting and "0" means no operation. Up/down pulse input UP DN 1 1 1 1 Note ) Both UP and DN should not be "0" at once. Phase-shifted pulse input A B Single 1 0 0 Double 1 0 1 Quad 1 1 1 Single pulse input A 0 0 1 0001 0101 1111 B Single 1 Double 1 0 1 1 1 00 10 0 0 0 0 0 0 Note ) B is used as the count enable signal. -9- (Z2044G00)ZENIC INC. www..com ZEN2044F 4-5. Detection of abnormal input The ZEN2044F has the function to check whether the phase-shifted pulse inputs show a correct transition state(shown in Fig.1 with mark) or not. When an abnormal transition state(shown in Fig.1 with mark) occurs, the Abnormal Input flag(D7 bit of the status register) is set. Some causes of the abnormal transition state are as follows: (1) The frequencies of phase shifted pulse inputs exceed the one fourth of the system clock frequency. In this case, the transition state cannot be sampled correctly. (2) When the line-noises are sampled, the ZEN2044F detects the abnormal transition. Fig.1 State transitions and an example of detecting the abnormal input AB 11 A 0 01 10 B 0 00 AI(00->11) 0 1 1 0 1 11 1 1 0 0 1 10 - 10 - (Z2044G00)ZENIC INC. www..com ZEN2044F 4-6. Default values of internal registers after reset After RESET is asserted, the values of the internal registers and the system mode are set according to Table 6. Table 6 Regsiter/Mode Counter Preload reg. The reset value 000000H keeping the value before reset keeping the value before reset Regsiter/Mode System mode Reference reg. A Reference reg. B The reset value Mode 0 keeping the value before reset keeping the value before reset Latch reg. Command reg. D7(LD) D6(ZE1) D5(ZE0) D4(LT) D3(RS1) D2(RS0) D1(BS1) D0(BS0) Status reg. D7(AI) D6(Z) D5(A) D4(B) D3(DTR) D2(U/D) D1(EQA) D0(U) 0 1 0 0 0 0 0 0 (NOP) ZNE (NOP) Up/down counter Low byte 0 Depending Depending Depending 0 0 1 Depending on input Z/CLR on input A/UP on input B/DN on input U 5. Registers The ZEN2044F has the following registers at each cannel. A A A A A command register for controling the action of the counter.[write only] status register for indicating the internal state.[read only] preload register for storing the counter value to be loaded.[write only] reference register for storing the value to be compared with the counter.[write only] latch register for storing the counter value to be read by the CPU.[read only] Note ) The counter value can be directly wrote without storing it in the preload register but we don't recommend it. ZEN2044F - 11 (Z2044G00)ZENIC INC. www..com 5-1. Access pointer Before you write a data to a certain register, you should set an access pointer properly. But the ZEN2044F has an auto-incremental function of the access pointer. So when you write data in the following sequence, what you have to set is only a starting point. Also when reading the latch register, the target byte(low, middle or high) is changed automatically. Fig.2 For writes Counter(low byte)[default at reset] Counter(middle byte) Counter(high byte) Reference reg.A(low byte) Reference reg.A(middle byte) Reference reg.A(high byte) Preload reg.(low byte) Preload reg.(middle byte) Preload reg.(high byte) In Mode 0 Reference reg.B(low byte) Reference reg.B(middle byte) Reference reg.B(high byte) In Mode 1 For reads Latch reg.(low byte)[default at reset] Latch reg.(middle byte) Latch reg.(high byte) - 12 - (Z2044G00)ZENIC INC. www..com ZEN2044F 5-2. System mode set command This is the command word to select system mode. If you use the conter in Mode 1, you need to write the Mode 1 select command at first because the Mode 0 is the default setting at reset. Table 6 Format of system mode set command D7 1 1 D6 0 0 D5 0 0 D4 1 1 D3 0 0 D2 0 0 D1 0 0 D0 0 1 HeX 90 91 Operation Mode 0 select[default] Mode 1 select (1) Mode 0[default] EXTAn is set as a comparator output (EQAn ) and EXTBn is set as a universal input U. (2) Mode 1 EXTBn is set as an output. Both EXTAn and EXTBn can be programed. Please refer to Mode1 register format in detail. 5-3. Command register format(common to Mode 0 and Mode 1) This is the command word for selecting register, selecting byte, latching counter, loading preloaded value and controling action of Z phase input. Table 7 Field format of command register(common to Mode 0 and Mode 1) D7 LD D6 ZE1 D5 ZE0 D4 LT D3 RS1 D2 RS0 D1 BS1 D0 BS0 BS1,BS0(Byte Select) The registers(preload, reference and latch) and the up/down counter have 24 bit length but the CPU bus is 8 bit in the ZEN2044F. The BS1 and BS0 determine the target byte(high byte, middle byte or low byte) when the CPU accesses ZEN2044F. RS1,RS0(Register Select) RS1 and RS0 specify the register to be accessed from among the three registers(preload, reference and latch) and the up/down counter. LT(Latch) This bit is used to store the value of the up/down counter into the latch register. ZE1, ZE0(Z phase input control) ZE1 and ZE0 control the way of clearing the counter by Z phase input. One of "ignoring", "once" or "every time" can be selected. LD(Load) This bit is used to transmit the data which is stored in the preload register to the up/down counter. Note 1) Do not execute Load and Latch operations at once. Note 2) When Load or Latch command is executed, the external pins, LT and LD , must be fixed at "1" . - 13 - (Z2044G00)ZENIC INC. www..com ZEN2044F Table 8 Format of command register D7 * * * * * * * * * * * * 0 0 1 1 1 D6 * * * * * * * * 0 0 1 1 * * * 0 * D5 * * * * * * * * 0 1 0 1 * * * 0 * D4 * * * * * * * * * * * * 0 1 0 1 1 D3 0 0 1 1 1 * * * * * * * * * * * * D2 0 1 * 0 1 * * * * * * * * * * * * D1 * * * * * 0 0 1 * * * * * * * * * D0 * * * * * 0 1 * * * * * * * * * * Operation Selecting up/down counter[default] Selecting reference reg. A Selecting preload reg.(in Mode 0) Selecting preload reg.(in Mode 1) Selecting reference reg. B(in Mode 1) Selecting low byte[default] Selecting middle byte Selecting high byte Keeping current setting as to Z phase input Setting Z phase pulse ineffective Setting only next Z phase pulse effective Setting every Z phase pulse effective No operation as to Load/Latch Latching the count value Loading the preload value Command ID Inhibit(except Command ID) Note 1) "*" stands for "don't care". Note 2) Command ID indicates system mode select or Mode 1 command. 5-4. Command register format(Mode 1) Only when the system mode is Mode 1, the command group of Mode 1 becomes effective. The reference register B can be accessed in Mode 1 only and the D0 of the status register shows the result of the comparator B. EXTAn can be programmed to output one of three signals(EQAn ,EQAn + EQBn or INTEQAn ). EXTBn can be programmed to output one of three signals(EQBn ,INTEQBn or INTAIn ). EQAn is the result of comparing the reference register A to the up/down counter. EQBn is the result of comparing the reference register B to the up/down counter. EQAn+EQBn is the logical sum(OR) of EQAn and EQBn . INTEQAn is the hold output of EQAn . INTEQBn is the hold output of EQBn . INTAIn is holding low once an abnormal transition state is detected. Above three hold outputs can be used for an interrupt request. And they have three functions, enabling, disabling and reset. AI reset command resets EXTBn output and initializes the phase discrimination circuit. ZEN2044F - 14 (Z2044G00)ZENIC INC. www..com Table 9 Format of command register(mode1) D7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F Operation Inhibit Inhibit EQAn + EQBn -> EXTAn EQAn -> EXTAn [default] Inhibit EQBn -> EXTBn [default] INTEQAn command reset INTEQBn , INTAIn command reset INTAIn -> EXTBn disabling INTAIn -> EXTBn enabling INTEQAn -> EXTAn disabling INTEQAn -> EXTAn enabling INTEQBn -> EXTBn disabling INTEQBn -> EXTBn enabling Note ) Both EXTAn and EXTBn cannot share an interrupt line with outputs of other IC because they don't have 3st output. ZEN2044F - 15 (Z2044G00)ZENIC INC. www..com 5-5. Status register The status register is used to monitor internal conditions. Please refer to "4-1. CPU Interface" for the method of reading out this register. Table 10 Format of status register Bit D7 Symbol AI Active High Description Abnormal input detection flag(only phase-shifted pulse input) A value of "1" indicates that the abnormal transition state of phase shifted inputs is detected. Z/CLRn input monitor This bit indicates the value of Z/CLRn input that is sampled at the rising edge of CLK. A/UPn input monitor This bit indicates the value of A/UPn input that is sampled at the rising edge of CLK. B/DNn input monitor This bit indicates the value of B/DNn input that is sampled at the rising edge of CLK. Data ready flag of the latch register A value of "1" indicates the counter data has been transfered to the latch register. This flag is cleared by reading the data of the latch register. Direction of counting The current counting direction is indicated. "1" means up count and "0" means down count. Coincident flag of comparator A A value of "0" indicates the data of counter and comparator A is coincident. Universal input U(EXTBn ) input monitor This bit indicates the value of EXTBn input. This signal is not sampled but directly monitored. Coincident flag of comparator B A value of "0" indicates the data of counter and comparator B is coincident. D6 Z None D5 A None D4 B None D3 DTR High D2 U/D None D1 EQA Low D0 U [Mode 0] EQB [Mode 1] None Low - 16 - (Z2044G00)ZENIC INC. www..com ZEN2044F 6. Internal timing(for reference only) The internal timings of the ZEN2044F are as follows. Note ) CNT stands for the value of the internal counter. LDR stands for the value of the preload register. LTR stands for the value of the latch register. CMPRA stands for the value of the reference register A. 6-1. Counting up/down 6-1-1. Two phase-shifted pulse mode(DIR="1") CLK A/UP B/DN CNT (x4) CNT (x2) CNT (x1) EXTB n n n n+1 n+2 n+3 n+4 n+3 n+2 n+1 n+1 n+2 n+1 n+1 n n n (When INTAI is enabled and AI is detected) 6-1-2. Single pulse mode(DIR="1") CLK A/UP B/DN CNT (x2) CNT (x1) 6-1-3. Up/down pulse mode(DIR="1") CLK A/UP B/DN CNT n n+1 n n n n+1 n+2 n+3 n+1 n+4 n+2 ZEN2044F - 17 (Z2044G00)ZENIC INC. www..com 6-2. Clearing counter 6-2-1. Asynchronous mode(Detecting the rising edge of Z/CLR) CLK Z/CLR CNT counting up/down 0 counting up/down 6-2-2. Synchronous mode(Detecting the rising or falling edge of A/UP when Z/CLR is "1" and B/DN is "0") CLK A/UP B/DN Z/CLR CNT counting up/down 0 counting up/down 6-3. Loading or latching counter value 6-3-1. External loading or latching CLK LD LT LDR CNT LTR a n m a a ZEN2044F - 18 (Z2044G00)ZENIC INC. www..com 6-4. Detecting coincidence 6-4-1. Momentary coincident output CLK CMPRA CNT EXTA 6-4-2. Hold coincident output CLK CMPRA CNT EXTA Note ) EXTB has the same timing as EXTA in Mode 1. n n-1 n n+1 n-1 n n n+1 ZEN2044F - 19 (Z2044G00)ZENIC INC. www..com 7. Electrical specifications 7-1. Absolute maximum ratings Parameter Supply voltage Input voltage Output voltage Input current Storage temperature Symbol Vdd Vin Vout Iin Tstg Rating -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -10 to +10 -40 to +125 Unit V V V mA C 7-2. Recommended operating conditions Parameter Supply voltage Operation temperature Symbol Vdd Topr Min 4.75 0 Typ 5.00 Max 5.25 +70 Unit V C 7-3. DC chracteristics(at the recomended operating conditions) Parameter Input "High" voltage Input "Low" voltage Input "High" current Input "Low" current Output "High" voltage Output "Low" voltage Standby current Operation current Symbol Vih Vil Iih Iil Voh Vol Idds Iddo Vin=Vdd Vin=Vss Ioh=-4mA Iol=4mA Vin=Vdd or Vss -10 -10 2.4 0.4 17 60 Conditions Min 2.2 0.8 10 10 Max Unit V V uA uA V V uA mA Note ) Ioh is Output "High" current and Iol is Output "Low" current. ZEN2044F - 20 (Z2044G00)ZENIC INC. www..com 7-4. AC chracteristics Parameter C/D,AD/CEn setup time(to D7-D0) C/D,AD/CEn hold time(to D7-D0) Data setup time(to WR) Data hold time(to WR) WR pulse width WR recovery time[1] C/D,AD/CEn setup time(to RD) C/D,AD/CEn hold time(to RD) RD pulse width Data access time(from RD) Data float time(from RD) RD recovery time[1] Clock high/low pulse width Clock cycle time Reset pulse width Reset recovery time LDn pulse width LTn pulse width EXTBn set time(from CLK)[2] EXTBn float time(from CLK)[3] EXTAn , EXTBn fix time(from CLK) A/UPn, B/DNn cycle time[4] A/UPn, B/DNn high/low level time[4] A/UPn, B/DNn phase difference time[4] Z/CLRn high level width[5] Z/CLRn pulse width[6] A/UPn setup time(to B/DNn)[7] A/UPn high/low level time[7] A/UPn cycle time[7] A/UPn, B/DNn cycle time[8] A/UPn, B/DNn high/low level time[8] Symbol TAW TWA TDW TWD TWW TWRC TAR TRA TRR TRD TDF TRRC TCP TCY TRST TRSRC TLDW TLTW TSEB TFEB TEXF TCYAB TPWAB TSAB TSZ TZZ TSS TAHL TACY TUDCY TU TCY*4+32 TCY*2+16 TCY+8 TCY+8 TCY+8 TCY+8 TCY+8 TCY*2+16 TCY*2+16 TCY+8 4 TCY*5 15 30 TCY*2 TCY*5 25 25 15 15 15 Min 0 0 30 3 25 TCY*5 0 5 25 20 Max Unit nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS Note ) [1] Required interval clock cycles to access the ZEN2044F [2] At executing Mode 1 select command [3] At executing Mode 0 select command [4] Two phase-shfted pulse mode [5] Synchronous clear mode [6] Asynchronous clear mode [7] Single pulse mode [8] Up/down pulse mode ZEN2044F - 21 (Z2044G00)ZENIC INC. www..com 7-5. Timing diagrams 7-5-1. Two phase-shifted pulse input timing TCYAB TPWAB A/UPn TSAB B/DNn TPWAB TCYAB Z/CLRn (Synchronous clear mode) TPWAB TSAB TSAB TSAB TPWAB TSZ TSZ Z/CLRn (Asynchronous clear mode) TZZ 7-5-2. Single pulse input timing A/UPn TAHL TSS B/DNn 7-5-3. Up/down pulse input timing A/UPn TU TUDCY TUDCY TU B/DNn TU TU TACY TAHL ZEN2044F - 22 (Z2044G00)ZENIC INC. www..com 7-5-4. Write cycle timing C/D AD/CEn D7-D0 TAW TWA WR TWW TDW TWD TWRC 7-5-5. Read cycle timing C/D AD/CEn RD TAR TRR TRA TRRC D7-D0 TRD TDF 7-5-6. System clock timing CLK TCP TCP TCY 7-5-7. System reset timing RESET TRST TRSRC WR,RD LDn, LTn 7-5-8. Load pulse input timing LDn TLDW 7-5-9. Latch pulse input timing LTn TLTW ZEN2044F - 23 (Z2044G00)ZENIC INC. www..com 7-5-10. EXTAn , EXTBn output timing CLK EXTAn EXTBn TEXF CLK EXTBn TSEB Note ) At executing Mode 1 select command(EXTBn is changed from input into output) CLK EXTBn TFEB Note ) At executing Mode 0 select command(EXTBn is changed from output into input) 8. Package Outlines 23.8+-0.3 20.0+-0.2 0.825TYP 80 51 50 81 14.0+-0.2 100 31 0.13 M 0.65 2.7+-0.2 0.575TYP 1 0.3+-0.1 30 17.8+-0.3 3.05MAX 0.15 +0.1 0.15 -0.05 0-10deg. 0.8+-0.2 (Unit : mm) 0.19+-0.1 ZEN2044F - 24 (Z2044G00)ZENIC INC. www..com Note This document is the user manual for the ZEN2044F and all information is applicable for reference only. Copying the whole contents or any part of this document is strictly prohibited. ZENIC reserves the right to change or alter this information or prices of specfied products at any time without any notice. ZENIC advises its customers to obtain the latest version of device specifications. ZENIC does not assume any liability arising out of the application or use of any product or circuit described herein; nor does it convey any license under its patent right or the rights of others. ZENIC products are not designed, intended, or authrized for use as componets in systems intended for surgical implant into the body, or other applications inteded to support or sustain life, or for any other application in which the failure of the ZENIC products could create a situation where personal injury or death may occur. All rights reserved. Copyright 2000 ZENIC Inc. ZENIC Inc. URL http://www.zenic.co.jp/ 1-17-14, Ogaya Otsu Shiga 520-2144, JAPAN Fax. +81-77-543-9431 Phone. +81-77-543-2101 E-mail support@zenic.co.jp - 25 - (Z2044G00)ZENIC INC. |
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